搜索资源列表
aes_core
- AES高级加密算法的verilog语言实现。同时附有AES协议的pdf文档，和此代码的测试程序，可作为一个IP核直接使用，可减少开发人员的设计时间。-AES Advanced Encryption Algorithm Verilog language. While the agreement with AES pdf documents, and that this code of the test procedure can be used as an IP core direct use,
mini_aes
- aes算法的verilog hdl实现，供给大家作为参考 。-Orangk'aes algorithm verilog hdl realized, we supply as a reference.
aes_core
- Verilog实现AES加密算法 密码模块作为安全保密系统的重要组成部分，其核心任务就是加密数据。分组密码算法AES以其高效率、低开销、实现简单等特点目前被广泛应用于密码模块的研制中。密码模块一般被设计成外接在主机串口或并口的一个硬件设备或是一块插卡，具有速度快，低时延的特点。而从整体发展趋势来看，嵌入式密码模块由于灵活，适用于多种用户终端、通信设备和武器平台，将会得到更加广泛的应用
aes_core.tar
- AES的Verilog实现,用于加密的算法硬件实现!
AES_RTL
- 使用Verilog HDL 實現AES硬體加解密
FPGA-IMPLEMENTATION-OF-AN-AES-PROCESSOR
- Advanced Encryption Standard(AES) implementing in a faster and secured way is expected. AES can be implemented in software/hardware. In hardware implementation ASIC solution requires high cost and much design time while FPGA based implementation
aes
- contains AES doc with code in Verilog
AES
- It s AES codes which is written by verilog.
AES
- aes源码verilog带有仿真环境，可用于FPGA实现-aes verilog rtl
AES
- AES的加密解密verilog全部源代码-AES encryption and decryption verilog full source code
AES
- 这是一个AES加密算法的程序，适用verilog hdl语言写的-A AES ALGORITHM
aes-core-include-testbentch
- aes core的verilog代码，包含测试代码和波形文件-aes core verilog code including testbentch
aes
- 使用verilog的128位aes加密源程序-Use verilog of 128 aes encryption source code
aes
- 利用verilog实现AES加密功能，S盒的实现方式有两种，一种是查找表的方式，一种是计算的方式。-Use verilog implementation AES encryption, there are two kinds of S box is implemented, a way is look-up table , a way is calculation.
aes-master
- verilog code for AES encryption and decryption
aes_thesis_v1.0
- aes code in verilog vhdl language which is very useful.
apbtoaes128_latest.tar
- verilog实现的AES加解密程序，接口为APB总线。(AES encryption and decryption program implemented by Verilog)
AESj 加密解密Verilog
- 128位AES加密解密，可以在FPGA上实现
aes_128pprm3
- 基于PPRM3S盒的128位AES密码算法Verilog代码(Verilog code for 128 bit AES cipher based on PPRM3S box)
基于FPGA的AES256位加密
- aes 256位 算法 加密程序，使用verilog 语言(AES 256 bit algorithm encryption program, using Verilog language)